Source: Compiled and translated from semiconductor-digest

The transaction value of semiconductor mergers and acquisitions surged from $2.7 billion in 2023 to $45 billion in 2024, and this growth momentum has continued into 2026. But the changes are not just reflected in the numbers. The deals themselves have evolved; especially in the memory sector, acquirers are no longer chasing patent portfolios, but paying for wafer capacity and packaging access. The same logic is spreading outward: in advanced packaging, ownership of physical facilities has become the new competitive advantage; in power semiconductors, vertical integration from substrates to finished devices is the decisive deal strategy; in edge artificial intelligence, acquirers expand the entire design-to-deployment pipeline by purchasing inference processing power. The common thread is that artificial intelligence has made supply chain position the most valuable asset in the semiconductor industry, and the memory supercycle is the best embodiment of this shift.

Over the past few years, I have been closely following this industry and witnessed the real-time shift in due diligence priorities. This transformation began during the chip shortage of 2021–2022, which forced buyers to assess geographic risk exposure in their supply chains and gradually evolved. By 2023–2024, amid constraints on HBM and CoWoS, packaging lead times became the top concern, accelerating the transition. Today, the first question in nearly every deal is no longer “What about the IP portfolio?” but “What are the wafer supply commitments, and how long will they last?”

At the heart of this transformation is memory, and its impact is physical. Each gigabyte of high-bandwidth memory consumes roughly three times the wafer capacity of traditional DDR5, and HBM4 raises that ratio to well over 3:1. Through-silicon via (TSV) processing, wafer thinning, and advanced stacking techniques add production steps and reduce yields. Companies such as SK Hynix, Samsung, and Micron have dedicated cleanroom space to HBM production to meet this challenge, and the results are striking: by 2026, AI-related memory is expected to consume nearly 20% of the global DRAM wafer output, even as annual DRAM capacity growth remains only 10% to 15%. IDC describes this as a zero-sum game: every wafer allocated to HBM stacking means insufficient wafers for LPDDR5X modules in mid-range smartphones or solid-state drives (SSDs) in consumer laptops.

For deal teams, wafer supply constraints are not abstract production metrics but critical factors directly impacting target company valuations. When supply is structurally constrained, acquirers factor supply chain access into deal premiums because owning or controlling wafer allocation becomes a competitive advantage that no licensing agreement can replicate. The most significant change is where supply chain sits in the evaluation process. It is no longer a marginal risk adjustment factor but a valuation input from the very beginning. Long-term supply agreements are underwritten almost like contracted revenue backlogs, and packaging access is valued like a strong intellectual property portfolio.

Accelerating demand growth stems from more than just training workloads. As AI models grow more complex—with multimodal inference, long context windows, and chain-of-thought reasoning—the memory required per inference session is outpacing the scaling capacity of HBM or DRAM. Google researchers have warned that the fourfold increase in DRAM capacity that once took three to six years may now take a decade or more. Inference is shifting from compute-intensive to memory-intensive, creating an opportunity for NAND flash.

NAND flash holds structural advantages here, and semiconductor investors are only just beginning to recognize them. Unlike HBM or DRAM, NAND flash can scale across four dimensions simultaneously: vertical stacking (increasing layers, with current products reaching 321 layers), logic scaling (moving from TLC to QLC and beyond to increase bits per cell), lateral cell shrinking, and architectural scaling. Architectural scaling is the hallmark of so-called 4D NAND flash, which moves peripheral circuits such as page buffers and control logic beneath the 3D cell array rather than alongside it. Each dimension increases storage capacity per wafer without a corresponding rise in capital expenditure, allowing NAND flash to improve cost-per-bit at a rate unmatched by DRAM.

This is why technologies such as SanDisk’s High-Bandwidth Flash (HBF)—which stacks NAND chips using HBM-style packaging to deliver 16 times the capacity at comparable bandwidth and cost—are gaining attention from system architects and increasingly from acquirers taking a fresh look at memory hierarchies. When modeling long-term capacity trajectories for NAND manufacturers, layer count alone is a misleading input; it reflects only one of four independent scaling dimensions. Manufacturers that have transitioned to 4D architectures have effectively unlocked new dimensions of cost-per-bit improvement without commensurate capital spending. The distinction between manufacturers scaling vertically through brute force and those with room for architectural expansion is where roadmap differentiation should appear in final value assumptions, not just in technical appendices.

Supply constraints are most severe in memory, but the ripple effects are reshaping deal logic across the entire semiconductor value chain. The same pressures pushing memory acquirers to “capacity-centric” strategies are driving advanced packaging, power semiconductor, and edge AI companies into a wave of vertical integration. The logic remains consistent: when supply becomes the limiting factor, owning or controlling physical capacity becomes a competitive advantage that no licensing agreement can replicate.

Consider how this trend manifests across sectors. In advanced packaging, the most direct extension of memory bottlenecks, ASE Technology, the world’s largest OSAT provider, acquired a manufacturing fab from WIN Semiconductors in August 2025 for T$6.5 billion, purely to expand CoWoS and advanced packaging capacity for AI and high-performance computing (HPC) chips. When packaging access becomes the bottleneck limiting AI accelerator shipments, owning fabs is far more valuable than any supply agreement. In power semiconductors, Onsemi acquired Qorvo’s SiC JFET business for $115 million, strengthening its vertically integrated silicon carbide supply chain from wafer to packaged devices to power AI data centers. NXP Semiconductors acquired Kinara.ai for $307 million to add edge AI inference processing and extend its full design-to-deployment pipeline. All these deals, whether memory-related or not, reveal the same pattern: acquirers are buying up and down the supply chain, not horizontally.

Beyond these supply-side factors, geopolitical forces are accelerating industry consolidation. The CHIPS and Science Act fuels domestic semiconductor growth through tax incentives, subsidies, and grants aimed at supporting advanced manufacturing and supply chain localization. The expanded Advanced Manufacturing Investment Tax Credit—providing a 25% tax credit for semiconductor equipment and facility investments—is directing capital toward production in the U.S. and allied nations. Meanwhile, escalating export controls on advanced lithography, EDA software, and HBM products to China are creating a dual-track market. Western firms are willing to pay premiums for targets with secure domestic supply chains, while companies with significant exposure to the Chinese market face valuation discounts and regulatory uncertainty.

This bifurcation reinforces existing vertical integration trends. Due diligence now includes geographic supply chain risk assessment of target companies as a core workflow. Valuation models must account for regulatory risks in cross-border revenue streams. Post-merger integration planning increasingly involves restructuring supply chains to access government incentives. As a result, in today’s deal environment, geographic and policy factors interact with the same supply-side physical mechanics driving the memory supercycle: constrained capacity means every decision about where to manufacture, source, and package becomes a strategic bet with direct valuation impact.

The challenge unifying all these factors is that traditional valuation frameworks were not designed for supply-constrained markets. Standard discounted cash flow models assume future cash flows of semiconductor companies depend primarily on end-market demand and competitive positioning. Yet when supply itself becomes the constraint—whether the bottleneck is HBM wafer allocation, CoWoS packaging capacity, or SiC substrate availability—this assumption no longer holds. Deloitte projects global chip sales will reach $975 billion by 2026, with generative AI (GI) contributing roughly $500 billion—more than half of total revenue but less than 0.2% of total unit volume. When a tiny fraction of unit volume drives most economic value, traditional revenue multiple comparisons become misleading across every segment.

In practice, deal teams across the semiconductor supply chain are adapting in similar ways. Capacity-adjusted revenue multiples, valuation based on supply agreement duration, and scenario analysis around bottleneck resolution timelines have become standard deal tools. McKinsey notes that semiconductor industry consolidation and merger activity between computing platforms will likely continue through 2026, with acquirers prioritizing strategic control over data, AI models, and computing efficiency. The most successful acquirers are those that treat supply chain position as a core asset—not an operational detail to be optimized after closing, but a strategic factor integrated into deal modeling from the start.

What strikes me most about witnessing this transformation in real time is not the scale of the numbers but the persistence of the logic. Memory tightness was expected to be temporary; packaging bottlenecks were supposed to ease with TSMC’s CoWoS expansion; silicon carbide substrate shortages were meant to resolve as new fabs came online. None of this has happened. The memory supercycle makes clear that this is not a temporary price spike but a structural restructuring of the semiconductor value chain that has already changed which companies get acquired, at what price, and on what terms. Scarcity has simply moved higher up the chain, from wafers to packaging to substrates, with no sign of easing. For investors and operators navigating this environment, the key takeaway is this: the winners of the semiconductor M&A market over the next decade will be those who understand that in a supply-constrained world, the most valuable asset is not what you can design, but what you can manufacture, package, and deliver.

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